- Parallel and functional programming languages 

- Software Defined Radio

- Multiprocessor architectures

- DSP algorithms and hardware platforms

- SoC design

- Reconfigurable architectures

- Computer arithmetic

Reviewer, IEEE International Conference on Field Programmable Logic and Applications (FPL) 2006

Reviewer, IEEE International Symposium on System-on-Chip (SoC) 2007, 2008

Reviewer, Conference on Design, Automation and Test in Europe (DATE) 2008

Reviewer, International Solid State Circuits Conference (ISSCC) 2008

During my free time I enjoy reading, listening to music, watching movies, biking, playing videogames (mostly "adventures"), playing football or volleyball, playing guitar.

TEACHING ACTIVITIES:
- Teaching assistant at Tampere University of Technology (Fall semester 2004) for the course “Hardware Description Languages”, and teacher for the courses “Digital Design II” (Spring 2006 and spring 2007) and “Computer Architecture II” (spring 2007).
- Co-supervised 1 BSc and 6 MSc theses for the University of Bologna.

PREVIOUS WORKS:
- Design of a set of floating-point functional units for a TTA architecture.
- Design of a CAD configuration tool for a custom FPGA device developed with PERL language, to be used inside a chain of tools for the automatic configuration of a reconfigurable architecture, at the ST-Microelectronics/Arces joint laboratories.
- Design of a low-area occupation, embedded LUT RAM (0,18um technology, fully custom layout), in cooperation with STMicroelectronics.
- Design of a VHDL synthesizable model of a multiply-accumulate unit (MAC) to be attached to a RISC microprocessor.
- Implementation of a set of DSP algorithms on an embedded FPGA device.

1) “A system level IP integration methodology for fast SoC design”, Bocchi, M.; Brunelli, C.; De Bartolomeis, C.; Magagni, L.; Campi, F.; Proceedings from International Symposium on Systems-on-Chip, Tampere, Finland, 19-21 Nov 2003, pages 127-130
2) “A Reconfigurable FPU as IP component for SoCs”, Claudio Brunelli, Fabio Campi, Juha Kylliäinen, Jari Nurmi; Proceedings from International Symposium on Systems-on-Chip, Tampere, Finland, 16-18 Nov 2004, pages 103-106
3) “A Flexible Multiplier for Media Processing”, Claudio Brunelli, Perttu Salmela, Jarmo Takala, Jari Nurmi; Proceedings from SiPS’05 conference, Athens, Greece, 2-4 November 2005
4) “A FPGA Implementation of An Open-Source Floating-Point Computation System”, Claudio Brunelli, Fabio Garzia, Claudio Mucci, Fabio Campi, Davide Rossi, Jari Nurmi; Proceedings from International Symposium on Systems-on-Chip 2005, Tampere, Finland,  15-17 November 2005, pages 29-32
5) “NoC-Based Platform Implementation on FPGA”, T. Ahonen, J. Kylliäinen, C. Brunelli and Jari Nurmi; DATE 2006, Munich, Germany, 6-10 March 2006
6) “A VHDL Model and Implementation of a Coarse-Grain Reconfigurable Coprocessor for a RISC Core”, C.Brunelli, F.Cinelli, D.Rossi and J.Nurmi, Proceedings from PRIME 2006, Otranto, Italy, 12-15 Jun 2006, pages 229-232
7) “A Coarse-Grain Reconfigurable Machine With Floating-Point Arithmetic Capabilities”,Claudio Brunelli, Fabio Garzia, Jari Nurmi, Proceedings from ReCoSoC’06, Montpellier, France, 3-5 Jul 2006, pages 1-7
8) “Design and Verification of a VHDL Model of a Floating-Point Unit for a RISC Microprocessor”, Claudio Brunelli, Jari Nurmi, Proceedings from International Symposium on Systems-on-Chip, Tampere, Finland, 14-16 Nov 2006, pages 87-90
9) "Back-End Tool Flow For Coarse Grain Reconfigurable IP Block RAA", Tapio Ristimaki, Claudio Brunelli and Jari Nurmi, Proc. IP/SOC 2006, Grenoble, France,  6-7 December 2006, pag.201-206.
10) "Design of a C library for the implementation of 3D graphics applications on a SoC", Fabio Garzia, Claudio Brunelli, Juha Killiainen and Jari Nurmi, Proc. IP/SOC 2006, Grenoble, France, 6-7 December 2006, pag.371-374.
11) "Implementation of a Tracking Channel of a GPS receiver on a Reconfigurable Machine", Fabio Garzia, Claudio Brunelli, Lassi Nieminen, Riccardo Mastria and Jari Nurmi, Eurocon 2007, Warsaw, Poland, 9-12 Sept. 2007, pag.875--881.
12) “Co-processor Approach to Accelerating Multimedia Applications”, Claudio Brunelli and Jari Nurmi, Chapter from “Processor Design – System-on-Chip Computing for ASIC and FPGAs”, Springer
13) “Programming Tools for Reconfigurable Processors”, Claudio Mucci, Fabio Campi, Claudio Brunelli and Jari Nurmi, book chapter from “Processor Design – System-on-Chip Computing for ASIC and FPGAs”, Springer
14) “Implementation of a 2D Low-Pass Image Filtering algorithm on a reconfigurable device”, Fabio Garzia, Claudio Brunelli, Andrea Ferro and Jari Nurmi, ReCoSoC 2007, Montpellier, France, 18-20 June 2007, pag. 166-170.
15) F.Garzia, C. Brunelli, D. Rossi, J. Nurmi, "Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture", Proceedings of the 15th Reconfigurable Architecture Workshop (RAW 2008), Miami, Florida, USA, April 14-15 2008, pag.1-6.
16) C.Brunelli, F.Garzia and J.Nurmi, “A Coarse-Grain Reconfigurable Architecture for Multimedia Applications Featuring Subword Computation Capabilities”, Journal of Real-Time Image Processing, Springer.
17) C.Brunelli, F.Campi, C.Mucci, D.Rossi, T.Ahonen, J.Kylliäinen, F.Garzia, J.Nurmi, “Design Space Exploration of an Open-Source, IP-Reusable, Scalable Floating-Point Engine for Embedded Applications”, Elsevier Journal of System Architecture (to appear)
18) C.Brunelli, F.Campi, D.Picard, F.Garzia, “Reconfigurable Hardware: The Holy Grail of Matching Performance with Programming Productivity”, International Conference on Field-Programmable Logic and Applications (FPL08), Heidelberg, Germany, 8-10 September 2008.
19) C.Brunelli, F.Garzia, C.Giliberto, J.Nurmi, “A Dedicated DMA Logic Addressing a Time-Multiplexed Memory to Reduce the Effects of the System Bus Bottleneck”, International Conference on Field-Programmable Logic and Applications (FPL08), Heidelberg, Germany, 8-10 September 2008.
20) F.Garzia, C.Brunelli, C.Giliberto, R.Airoldi, J.Nurmi, “Implementation of W-CDMA Slot Synchronization on a Reconfigurable System-on-Chip”, International Symposium on System-on-Chip (SoC 2008), Tampere, Finland, 4-6 November 2008.
21) H.Berg, C.Brunelli, U.L ücking, “Analyzing Models of Computation for Software Defined Radio Applications”, International Symposium on System-on-Chip (SoC 2008), Tampere, Finland, 4-6 November 2008.