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Eero Aho

Senior Researcher - High Performance Mobile Systems
Tampere, Finland

 

I joined Nokia Research Center on 8/2007. I have worked on:

  • End-to-end connectivity quality with WLAN and cellular connections.
  • Applying native computing resources to web browser environment. WebCL standardization.
  • Parallel programming with OpenCL and WebGL for GPU (Graphics Processing Unit).
  • Research and definition of next generation high performance mobile terminal architecture and programming model.
  • Transaction level modeling of multichannel system memory architecture.
  • Video encoder and memory load modeling.

I worked for Institute of Digital and Computer Systems at Tampere University of Technology during 5/1999 - 7/2007. I made my PhD thesis on parallel memory architectures. My tasks have concentrated on:

  • Project coordination to publish a public video clip archive for benchmarking purposes
  • Research on parallel memories in parallelized video and image processing applications. Familiar with standards like JPEG, MPEG-4, H.263, H.264
  • Digital system design (ASIC and FPGA)
  • Embedded computing and HW/SW co-design

Research Projects

Tampere University of Tehcnology, DACI research group

Conferences

Publications in international conferences with review process (14)

  1. C. Brunelli, E. Aho, and H. Berg, “OpenCL implementation of Cholesky Matrix Decomposition,” In Proceedings of the International Symposium on System-on-Chip (SoC), Tampere, Finland, October 2011, pp. 62-67.
  2. E. Aho, K. Kuusilinna, and J. Nikara, “Memory Access Characteristics of H.264 Video Encoder on Embedded Processor,” In Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS), Tampere, Finland, October 2009, pp. 255-260.
  3. J. Nikara, E. Aho, P. A. Tuominen, and K. Kuusilinna, “Performance Analysis of Multi-Channel Memories in Mobile Devices,” In Proceedings of the International Symposium on System-on-Chip (SOC), Tampere, Finland, October 2009, pp. 128-131.
  4. E. Aho, J. Nikara, P. A. Tuominen, and K. Kuusilinna, “A Case for Multi-Channel Memories in Video Recording,” In Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Nice, France, April 2009, pp. 934-939.
  5. E. Aho, J. Vanne, and T. D. Hämäläinen, “Parallel Memory Implementation for Arbitrary Stride Accesses,” In Proceedings of the Embedded Computer Systems: Architectures, MOdeling, and Simulation Conference (IC-SAMOS), Samos, Greece, July 2006, pp. 1-6.
  6. E. Aho, J. Vanne, and T. D. Hämäläinen, “Parallel Memory Architecture for Arbitrary Stride Accesses,” In Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Prague, Czech Republic, April 2006, pp. 65-70.
  7. E. Aho, J. Vanne, T. D. Hämäläinen, and K. Kuusilinna, “Block-Level Parallel Processing for Scaling Evenly Divisible Frames,” In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005, pp. 1134-1137.
  8. J. Vanne, E. Aho, K. Kuusilinna, and T. Hämäläinen, “Enhanced Configurable Parallel Memory Architecture,” In Proceedings of the Euromicro Symposium on Digital System Design (DSD), Dortmund, Germany, September 2002, pp. 28-35.
  9. E. Aho, J. Vanne, K. Kuusilinna, and T. Hämäläinen, “Access Format Implementations in Configurable Parallel Memory,” In Proceedings of the International Conference on Computer and Information Science (ICIS), Seoul, Korea, August 2002, pp. 59-64.
  10. E. Aho, J. Vanne, K. Kuusilinna, and T. Hämäläinen, “XOR-scheme Implementations in Configurable Parallel Memory,” In Proceedings of the International Workshop on System-on-Chip for Real-Time Applications (IWSOC), Banff, Canada, July 2002, pp. 287-298.
  11. J. Vanne, E. Aho, K. Kuusilinna, and T. Hämäläinen, “Configurable Parallel Memory Implementation for System-on-Chip Designs,” In Proceedings of the International Workshop on System-on-Chip for Real-Time Applications (IWSOC), Banff, Canada, July 2002, pp. 253-264.
  12. E. Aho, J. Vanne, K. Kuusilinna, and T. Hämäläinen, “Diamond Scheme Implementations in Configurable Parallel Memory,” InProceedings of the IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Brno, Czech Republic, April 2002, pp. 211-218.
  13. J. Vanne, E. Aho, K. Kuusilinna, and T. Hämäläinen, “Co-Simulation of Configurable Parallel Memory Architecture and Processor,” InProceedings of the IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Brno, Czech Republic, April 2002, pp. 310-313.
  14. E. Aho, J. Vanne, K. Kuusilinna, T. Hämäläinen, and J. Saarinen, “Configurable Address Computation in a Parallel Memory Architecture,” In Proceedings of the WSES International Conference on Circuits, Systems, Communications and Computers (CSCC), Rethymnon, Greece, July 2001, pp. 4941-4946.

Publications

 Monographs (2)

  1. E. Aho, Design and Implementation of Parallel Memory Architectures, Dr. Tech. Thesis, Tampere University of Technology, Tampere, Finland, 2006, p. 191.
  2. E. Aho, Design of Address Computation in Configurable Parallel Memory, M.Sc. Thesis, Tampere University of Technology, Tampere, Finland, 2001, p. 62.

Publications in international journals with review process (8)

  1. J. Vanne, E. Aho, K. Kuusilinna, and T. D. Hämäläinen, “A Configurable Motion Estimation Architecture for Block-Matching Algorithms,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 19, No. 4, April 2009, pp. 466-477.
  2. J. Vanne, E. Aho, T. D. Hämäläinen, and K. Kuusilinna, “A Parallel Memory System for Variable Block Size Motion Estimation Algorithms,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 18, No. 4, April 2008, pp. 538-543.
  3. E. Aho, J. Vanne, and T. D. Hämäläinen, “Configurable Data Memory for Multimedia Processing,” Journal of Signal Processing Systems, Vol. 50, No. 2, February 2008, pp. 231-249.
  4. E. Aho, J. Vanne, T. D. Hämäläinen, and K. Kuusilinna, “Configurable Implementation of Parallel Memory Based Real-Time Video Downscaler,” Microprocessors and Microsystems, Vol. 31, No. 5, August 2007, pp. 283-292.
  5. J. Vanne, E. Aho, T. D. Hämäläinen, and K. Kuusilinna, “A High-Performance Sum of Absolute Difference Implementation for Motion Estimation,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, No. 7, July 2006, pp. 876-883.
  6. E. Aho, J. Vanne, T. D. Hämäläinen, and K. Kuusilinna, “Block-Level Parallel Processing for Scaling Evenly Divisible Images,” IEEE Transactions on Circuits and Systems I, Vol. 52, No. 12, December 2005, pp. 2717-2725.
  7. E. Aho, J. Vanne, K. Kuusilinna, and T. D. Hämäläinen, “Comments on “Winscale: An Image-Scaling Algorithm Using an Area Pixel Model”,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 15, No. 3, March 2005, pp. 454-455.
  8. E. Aho, J. Vanne, K. Kuusilinna, and T. D. Hämäläinen, “Address Computation in Configurable Parallel Memory Architecture,” IEICE Transactions on Information and Systems, Vol. E87-D, No. 7, July 2004, pp. 1674-1681.

 Book chapters (4)

  1. J. Nikara, T. Aarnio, E. Aho, and J. Pietiäinen, "WebCL," In Heterogeneous Computing with OpenCL, B. R. Gaster, L. Howes, D. R. Kaeli, P. Mistry, and D. Schaa, Morgan Kaufmann, Waltham, MA, USA, 2011, pp. 255-269.
  2. E. Aho, J. Vanne, K. Kuusilinna, and T. Hämäläinen, “XOR-scheme Implementations in Configurable Parallel Memory,” In System-on-Chip for Real-Time Applications,W. Badawy and G. A. Jullien, ed., Kluwer Academic Publishers, Boston, USA, 2003, pp. 249-261.
  3. J. Vanne, E. Aho, K. Kuusilinna, and T. Hämäläinen, “Configurable Parallel Memory Implementation for System-on-Chip Designs,” In System-on-Chip for Real-Time Applications,W. Badawy, and G. A. Jullien, ed., Kluwer Academic Publishers, Boston, USA, 2003, pp. 237-248.
  4. E. Aho, J. Vanne, K. Kuusilinna, T. Hämäläinen, and J. Saarinen, “Configurable Address Computation in a Parallel Memory Architecture,” In Advances in Signal Processing and Computer Technologies, G. Antoniou, N. Mastorakis, and O. Panfilov, ed., WSES Press, Athens, Greece, 2001, pp. 390-395.

Patents

Over ten patens pending