John Shen

Background

I lead the System Research Center in Nokia Research Center Palo Alto. Prior to joining Nokia in 2006, I was the Director of the Microarchitecture Research Lab at Intel, which was responsible for developing innovative microarchitecture and system architecture techniques that can be incorporated in microprocessor products and platforms from Intel. My teams of researchers (located in Santa Clara CA, Austin TX, and Hillsboro OR) worked closely and effectively with product development teams to create innovative technologies in the areas of out-of-order superscalar processors, speculative multithreading and memory prefetching, 3D die-stacking technology and architecture, and heterogeneous multi-sequencer architectures.

Prior to joining Intel in 2000, I was a Professor in the Electrical and Computer Engineering Department of Carnegie Mellon University, where I supervised a total of 17 PhD students and numerous MS students and received multiple teaching awards.

I received my BS degree from the University of Michigan and my MS and PhD degrees from the University of Southern California, all in Electrical Engineering. I am very happily married and have three active teenage daughters.

Professional Activities

I have helped organize several leading conferences, including ASPLOS (general chair), MICRO (program chair), PACT (program chair), and FTCS (general chair), and served on the program committee of numerous conferences and workshops. I am an IEEE Fellow and have published 120 research papers covering a diverse aray of topics.

Publications

Books

1. J.P. Shen and M.H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, Beta Edition, McGraw-Hill 2003.
2. J.P. Shen and M.H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, First Edition, McGraw-Hill 2005.

Book Chapters

1. D.P. Siewiorek, J.P. Shen, and R.A. Maxion, "Experimental Research in Reliable Computing at Carnegie Mellon University," in The Evolution of Fault-Tolerant Computing, A. Avizienis, H. Kopetz, and J.C. Laprie (eds.), Springer-Verlag, 1987.
2. R.P. Bianchini, Jr. and J.P. Shen, "Network Traffic Scheduling Algorithm for Application-Specific Architectures," Concurrent Computations: Algorithm, Architecture and Technology, S.K. Tewksbury, B.W. Dickinson and S.C. Schwartz (eds.), Plenum Press, July 1988.

Articles

More than 100.

Patents

4 patents issued:

1. 6,668,306 - NON-VITAL LOADS (issued: 12/23/2003)
2. 6,928,645 - SOFTWARE-BASED SPECULATIVE PRE-COMPUTATION AND MULTITHREADING (8/9/2005)
3. 6,954,848 - MARKING IN HISTORY TABLE INSTRUCTIONS SLOWABLE / DELAYABLE FOR SUBSEQUENT EXECUTIONS WHEN RESULT IS NOT USED IMMEDIATELY (10/11/2005)
4. 6,938,126 - CACHE-LINE REUSE-BUFFER (8/30/2005)

55 patents pending.