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Quinn Jacobson

Research Leader
Palo Alto

Dr. Jacobson is a Research Leader at Nokia Research Center – Palo Alto. He is currently starting a new effort to investigate next generation High Performance Mobile Platforms. Trying to identify, and if necessary invent, the building blocks that will define the next killer device.

 

When Dr. Jacobson joined Nokia in 2006 he built and led the Mobile Internet Services Systems team.  The team ran the TrafficWorks project, aimed at making traffic data more usable by commuters through traffic-aware routing algorithms, innovative ways to personalize traffic information and new approaches to dynamic traffic alerts. This project leveraged the team’s prior work on how best to collect and process real-time traffic flow data from GPS-enabled mobile phones while protecting phone users’ privacy.

 

Much of the technology created by through the TrafficWorks project has influenced the LBS product line in Nokia’s subsidiary Navteq. The TrafficWorks project also contributed to the Mobile Millennium pilot and the related Connected Traveler work. This was a joint effort by Nokia, Navteq, Caltrans and UC Berkeley that was part of the SafeTrip-21 Initiative of the IntelliDrive Program. Dr. Jacobson served as the Principal Investigator from Nokia in the company’s partnerships supporting the U.S. Department of Transportation’s IntelliDrive program.

Prior to joining NRC Palo Alto in 2006, Dr. Jacobson headed an exploration within Intel’s Microarchitecture Research Lab into architectural features for making parallel programming more efficient and robust. Prior to Intel, he was the chief architect for Sun Microsystems’ UltraSPARC IV family of processors, Sun’s first family of multicore processors. Quinn received his Ph.D. in Electrical and Computer Engineering from the University of Wisconsin – Madison and holds over two dozen issued patents.

Publications

  • L. Leem, H. Cho, J. Bau, Q. Jacobson and S. Mitra, “ERSA: Error-Resilient System Architecture for Probabilistic Applications,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.

  • Y. Wang, J. Lin, M. Annavaram, Q. Jacobson, J. Hong, B. Krishnamachari, N. Sadeh, “A Framework of Energy Efficient Mobile Sensing for Automatic Human State Recognition,” to appear in Proceedings of the 7th International Conference on Mobile System, Applications, and Services (MobiSys 2009).

  • D. Work, O.-P. Tossavainen, Q. Jacobson, A. Bayen,  ”Lagrangian Sensing: Part II Distributed Traffic Estimation with Mobile Devices,” to appear in the proceedings of the ACC 2009 - 2009 American Control Conference.

  • B. Hoh, et. al.,"Virtual Trip Lines for Distributed Privacy-Preserving Traffic Monitoring," submitted to the Sixth International Conference on Mobile System, Applications, and Services (MobiSys 2008).

  • B. Saha, A. Adl-Tabatabai, Q. Jacobson, "Architecture Support for Software
    Transactional Memory," in Proceedings of the 39th Annual International
    Symposium on Microarchitecture, December 2006.
  • Q. Jacobson, "Sun Microsystems' UltraSPARC IV Processors," in
    Proceedings of the 2003 Microprocessor Forum, October 2003
  • Q. Jacobson, J. E. Smith, "Trace Preconstruction," in Proceedings of the
    27th International Symposium on Computer Architecture, June 2000.
  • L. Fan, P. Cau, W. Lin, Q. Jacobson, "Web Prefetching between Low-Bandwidth
    Clients and Proxies: Potential and Performance," in proceedings of SIGMETRICS 1999.
  • Q. Jacobson, J. E. Smith, "Instruction Pre-Processing in Trace
    Processors," in Proceedings of the 5th International Symposium on
    High-performance Computer Architecture, January 1999.
  • E. Rotenberg, Q. Jacobson, J. E. Smith, "A Study of Control Independence
    in Superscalar Processors," in Proceedings of the 5th International
    Symposium on High-performance Computer Architecture, January 1999.
  • Q. Jacobson and P. Cao, "Potential and Limits of Web Prefetching Between
    Low-Bandwidth Clients and Proxies," presented at the 3rd International
    WWW Caching Workshop, Manchester, England, June 1998.
  • A. Varma and Q. Jacobson, "Destage Algorithms for Disk Arrays with
    Non-Volatile Caches," IEEE Transactions on Computers, February 1998.
  • Q. Jacobson, E. Rotenberg, J. E. Smith, "Path-Based Next Trace
    Prediction," in Proceedings of the 30th International Symposium on
    Microarchitecture, December 1997.
  • E. Rotenberg, Q. Jacobson, Y. Sazeides, J. E. Smith, "Trace Processors,"
    in Proceedings of the 30th International Symposium on Microarchitecture,
    December 1997. (Best Paper Award)
  • Q. Jacobson, E. Rotenberg, J. E. Smith, "Future Generation Processors:
    Using Hierarchy and Replication," in Proceedings of the 1st
    International Workshop on Innovative Architecture, October 1997.
  • Q. Jacobson, S. Bennett, N. Sharma and J. E. Smith, "Control Flow
    Speculation in Multiscalar Processors," in Proceedings of the 3rd
    International Symposium on High-Performance Computer Architecture,
    February 1997.
  • A. Varma and Q. Jacobson, "Destage Algorithms for Disk Arrays with
    Non-Volatile Caches," in Proceedings of the 22nd Annual International
    Symposium on Computer Architecture, June 1995.
  • A. Varma, L. Kalampoukas, D. Stiliadis, and Q. Jacobson, "The CPU Design
    Kit: An Instructional Prototyping Platform for Teaching Processor
    Design," presented at the 1995 Workshop on Computer Architecture
    Education, Santa Margherita Ligure, Italy, June 1995.