Quinn Jacobson

Quinn leads the Mobile Internet Services Systems team at the Nokia Research Center - Palo Alto. His expertise is in architecting and prototyping mobile services, including privacy and security related challenges. Over the last year Quinn has been leading an effort to look at how to construct collaborative services, where individuals can share information in real-time, while preserving privacy.

Quinn Jacobson joined NRC Palo Alto in October 2006. Before joining Nokia Quinn worked in Intel’s Microarchitecture Research Lab, and before that Quinn was the chief architect for Sun Microsystems’ UltraSPARC IV family of processors. Quinn holds a Ph.D. in Electrical and Computer Engineering from the University of Wisconsin - Madison.

Representative Publications

• B. Hoh, et. al.,"Virtual Trip Lines for Distributed Privacy-Preserving Traffic Monitoring," submitted to the Sixth International Conference on Mobile System, Applications, and Services (MobiSys 2008).
• B. Saha, A. Adl-Tabatabai, Q. Jacobson, "Architecture Support for Software
  Transactional Memory," in Proceedings of the 39th Annual International
  Symposium on Microarchitecture, December 2006.
• Q. Jacobson, "Sun Microsystems' UltraSPARC IV Processors," in
  Proceedings of the 2003 Microprocessor Forum, October 2003
• Q. Jacobson, J. E. Smith, "Trace Preconstruction," in Proceedings of the
  27th International Symposium on Computer Architecture, June 2000.
• L. Fan, P. Cau, W. Lin, Q. Jacobson, "Web Prefetching between Low-Bandwidth
  Clients and Proxies: Potential and Performance," in proceedings of SIGMETRICS 1999.
• Q. Jacobson, J. E. Smith, "Instruction Pre-Processing in Trace
  Processors," in Proceedings of the 5th International Symposium on
  High-performance Computer Architecture, January 1999.
• E. Rotenberg, Q. Jacobson, J. E. Smith, "A Study of Control Independence
  in Superscalar Processors," in Proceedings of the 5th International
  Symposium on High-performance Computer Architecture, January 1999.
• Q. Jacobson and P. Cao, "Potential and Limits of Web Prefetching Between
  Low-Bandwidth Clients and Proxies," presented at the 3rd International
  WWW Caching Workshop, Manchester, England, June 1998.
• A. Varma and Q. Jacobson, "Destage Algorithms for Disk Arrays with
  Non-Volatile Caches," IEEE Transactions on Computers, February 1998.
• Q. Jacobson, E. Rotenberg, J. E. Smith, "Path-Based Next Trace
  Prediction," in Proceedings of the 30th International Symposium on
  Microarchitecture, December 1997.
• E. Rotenberg, Q. Jacobson, Y. Sazeides, J. E. Smith, "Trace Processors,"
  in Proceedings of the 30th International Symposium on Microarchitecture,
  December 1997. (Best Paper Award)
• Q. Jacobson, E. Rotenberg, J. E. Smith, "Future Generation Processors:
  Using Hierarchy and Replication," in Proceedings of the 1st
  International Workshop on Innovative Architecture, October 1997.
• Q. Jacobson, S. Bennett, N. Sharma and J. E. Smith, "Control Flow
  Speculation in Multiscalar Processors," in Proceedings of the 3rd
  International Symposium on High-Performance Computer Architecture,
  February 1997.
• A. Varma and Q. Jacobson, "Destage Algorithms for Disk Arrays with
  Non-Volatile Caches," in Proceedings of the 22nd Annual International
  Symposium on Computer Architecture, June 1995.
• A. Varma, L. Kalampoukas, D. Stiliadis, and Q. Jacobson, "The CPU Design
  Kit: An Instructional Prototyping Platform for Teaching Processor
  Design," presented at the 1995 Workshop on Computer Architecture
  Education, Santa Margherita Ligure, Italy, June 1995.