John Paul Shen

Head of Nokia Research North America
Palo Alto (recently moved to Sunnyvale)

John Paul Shen is the founding director of Nokia Research Center – North America Lab (formerly NRC Palo Alto) with research teams located in Palo Alto CA, Berkeley CA, and Cambridge MA pursuing a wide range of research projects in mobility and computing.

  • There are ~70 researchers and ~20 staff and interns working in NRC-NAL. Research teams are formed organically and are given significant autonomy. These innovation teams are highly agile with superb experimental and implementation skills, and are expected to go deep into the technology transfer pipeline in collaboration with product groups.
  • The primary mission for NRC-NAL is to help renew and transform Nokia into a major player in the new mobile convergence space through innovation in diverse domains. The current convergence in the industry involves the devices dimension (PC’s, mobile phones, and tablets) as well as the fabrics dimension (Internet and cellular networks). To succeed in the convergence space requires integrated innovations spanning HW, SW, services and ecosystems, as well as speed and agility in the execution of turning innovations into compelling products.
  • There are currently 10 teams in NRC-NAL pursuing research and advanced development in diverse areas, including: next-generation mobile computing devices, mobile web-based applications and services, end-to-end energy and performance efficiency, mobile user context sensing and data analytics, mobile internet services for emerging markets, automotive solutions with car as a mobile platform, imaging and computational photography, and mixed and augmented reality.

Prior to joining Nokia in 2006, John was the Director of the Microarchitecture Research Lab at Intel, which was responsible for developing innovative microarchitecture and system architecture techniques that can be incorporated in microprocessor products and platforms from Intel. Three teams of researchers (located in Santa Clara CA, Austin TX, and Hillsboro OR) worked closely and effectively with product development teams to create innovative technologies in the areas of out-of-order superscalar processors, speculative multithreading and memory prefetching, 3D die-stacking technology and architecture, and heterogeneous multi-core architectures.

Prior to joining Intel in 2000, John was a Professor in the Electrical and Computer Engineering Department at Carnegie Mellon University, where he supervised a total of 17 PhD students and numerous MS students and received multiple teaching awards. He is currently an adjunct professor at the CMU Silicon Valley campus, and has co-taught the Advanced Computer Architecture course at Stanford University.

John received his BS degree from the University of Michigan and his MS and PhD degrees from the University of Southern California, all in Electrical Engineering. He is very happily married and has three amazing daughters, two at UC Berkeley (Go Bears!) and one at Valley Christian High School in San Jose.

Professional Activities

John has helped organize several leading conferences, including ASPLOS (general chair), MICRO (program chair), PACT (program chair), and FTCS (general chair), and served on the program committee of numerous conferences and workshops. He is an IEEE Fellow and has published over 100 research papers covering a diverse array of topics.



  1. J.P. Shen and M.H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, Beta Edition, McGraw-Hill 2003.
  2. J.P. Shen and M.H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, First Edition, McGraw-Hill 2005.

Book Chapters

  1. D.P. Siewiorek, J.P. Shen, and R.A. Maxion, "Experimental Research in Reliable Computing at Carnegie Mellon University," in The Evolution of Fault-Tolerant Computing, A. Avizienis, H. Kopetz, and J.C. Laprie (eds.), Springer-Verlag, 1987.
  2. R.P. Bianchini, Jr. and J.P. Shen, "Network Traffic Scheduling Algorithm for Application-Specific Architectures," Concurrent Computations: Algorithm, Architecture and Technology, S.K. Tewksbury, B.W. Dickinson and S.C. Schwartz (eds.), Plenum Press, July 1988.


More than 100.



15 patents issued.

44 patents pending.